Transition Vector Reduction using Segmentation method based on Compression Technique

Present complexity of System on Chip (SoC) design is increasing rapidly in the number of test patterns, huge switching activity and its transition time. This large test data volume is becoming one of the major problems in association with huge switching activity and its corresponding response time. This paper considers the problem of huge test pattern and its switching activity in scan based design. This proposed algorithm is based on reducing test pattern and its huge switching activity on scan shift in operation. This is achieved by equally segmenting the scan based test patterns and identifying test data transition inside the segment. Each scan test pattern is considered by its transition and segmented into equal necessary blocks. This reduces test pattern and overall switching activity of the flip-flop in the design. Theoretical analysis and experimental results on ISCAS89 shows that the proposed method reduces test pattern by 37% and total switching activity by 75% when compared to the traditional approaches.